Class-D amplifiers utilise a switch element which is either fully on or off and which is switched at a high frequency with a duty cycle that is proportional to the amplitude of the input signal. This series of pulses is then applied to a low pass filter to provide an analogue output which corresponds to the input signal to the switch element. This analogue signal can then be applied to a speaker system for example.
The input to a Class-D amplifier is a series of digital words representing signal amplitude levels over time. A sigma-delta modulator or similar is typically used to convert these words into a series of bits or on/off pulses suitable for switching the switching element. FIG. 1 shows a schematic of a Class-D amplifier comprising an over-sampling filter 1, a modulator 2, a power switch 3, a low pass filter 4, and a headphone or loudspeaker load 5.
The over-sampling or interpolation filter adds additional samples from the incoming audio source samples by interpolating between the actual samples, thereby effectively increasing the sampling rate as is known. The over-sampled audio signal is fed to a modulator 2 such as a sigma-delta modulator. The modulator converts the signal into a one-bit output signal, the input signal modulating the output pulse density in the case of a sigma-delta modulator. The modulator also acts as a noise shaper moving in-band noise out of band. The series of pulses or bits control the power switch 3 which switches a much larger output voltage into a low pass filter 4 which turns this signal into an analogue signal as known for applying to the headphone or speaker load 5.
FIG. 2 shows a schematic of a sigma-delta modulator (SDM) comprising a quantizer Q and a loop filter H(z) in a feedback loop. The quantizer Q outputs a series of ones and zeros (1-bit, pulse or no pulse) depending on the level of its input value. The loop filter has high gain at low frequencies and is typically implemented as a low pass filter function such as an integrator for example. The SDM employs feedback around quantizer Q, so that the quantization noise power introduced into the baseband by the quantizing action of the quantizer is reduced, at the expense of greater noise power out of band.
A disadvantage of such amplifiers is that a zero or idle input signal requires the switching element to toggle between its maximum positive and negative output levels in order to maintain an average output level of zero. This results in high power dissipation in the switch. One approach to reducing this is to use bit-flipping in which some of the bits in the bit stream fed to the switch are flipped (ie changed from 1 to 0, or from 0 to 1) such that in the idle input signal situation for example, an average of zero is maintained but at a lower switching frequency. Thus a bit stream comprising: 1,0,1,0,1,0,1,0,1,0. . . is altered to: 1,1,1,0,0,0,1,1,1,0, . . . .
FIG. 3 shows conceptually a bit-flipping modulator having a Quantizer Q, a loop filter H(z), a pulse inversion unit BF and a control unit C to determine when to flip the quantizer output. The quantizer is used to requantize the incoming 16-bit (or greater) wordlength into a 1-bit word to control the power switch. In common with “standard” (i.e. non bit-flipping) SDMs, the loop filter provides high gain over the baseband and by feedback action, attenuates the noise introduced by the quantizer in the baseband. The BF controller controls operation of the BF Unit, so that it inverts the state of the quantiser when this will reduce the transition rate of the bitstream.
FIG. 4 shows the circuit structure of a practical bit-flipping sigma-delta modulator in detail. The circuit comprises look ahead modifications including a look ahead quantizer Q1a and a delay element z−1 between the input of the main quantizer Q and the input of the look ahead quantizer Q1a. Thus the current (Q) and next (Q1a) quantizer outputs are fed to the bit flipping control unit C.
The look-ahead modifications are needed by the bit-flipping control unit C to determine whether flipping the current quantizer Q output will reduce the transitions in the bit sequence. For example, if the quantizer Q output contains a bit pattern with previous, current and next outputs {1, 0, 0}, flipping the current quantizer output from 0 to 1 to produce pattern {1, 1, 0} will not reduce the transition rate. However the stability and SNR of the modulator will deteriorate. By predicting the next quantizer output, unnecessary bit-flipping can be avoided.
The feedback is taken from the output of the quantizer Q before the bit flipping unit BF, and thus the BF unit is taken out of the feedback loop. This is because the output of the look ahead quantizer Q1a must depend on the output of the quantizer Q (because of the feedback loop). If this were not the case, and all the feedback is taken from the bit flipping output, the look ahead quantizer output Q1a will depend directly on quantizer Q output, however the quantizer Q output depends on whether a decision is made to flip, which in turn depends on the output of the look ahead quantizer Q1a. Hence there would be a dependency loop (delay-free loop) which cannot be implemented in practice. When the loop is taken from the output of the quantizer Q, the look ahead quantizer output Q1a is calculated from the current quantizer Q output, rather than the bit-flipping output. Thus, the output of the look ahead quantizer Q1a is the equivalent to the next value of the quantizer Q when no bit flipping occurs on the current quantizer Q output.
In order to accommodate the situation where bit flipping of the quantizer Q output does occur, further modifications within the sigma delta modulator circuit are required. Because bit flipping on the current sample will affect the next quantizer Q state (because of the feedback loop), the input to the quantizer Q is modified by the BF compensation circuit (BFcomp) shown whenever the previous quantizer Q output has been flipped. The BF compensation circuit (BFcomp) comprises a multiplexor or switch (M) which switches in an adder (A) which introduces an appropriate compensation signal (pulse) into the quantizer's Q input signal whenever the quantizer's Q output has been flipped by the bit flipping unit BF.
The loop filter H(z) also contains modifications over an equivalent loop filter in a non-BF SDM in order to implement the look-ahead algorithm. If a decision is made to flip the quantizer Q output, the state of the filter H(z) needs modifying since the loop filter has already responded to the quantizer's unflipped Q output. A modified filter is shown in FIG. 5.
More information on bit-flipping can be found in Anthony J. Magrath and Mark B. Sandler. “Digital Power Amplification Using Sigma-Delta Modulation and Bit-Flipping”. Journal of the Audio Engineering Society, Volume 45, No. 6 Jun. 1997.